1. Field of the Invention
The present invention generally relates to a DC-DC converter. More specifically, the present invention relates to an active clamp DC-DC converter.
Priority is claimed on Japanese Patent Application No. 2005-286974, filed Sep. 30, 2005, the content of which is incorporated herein by reference.
2. Description of the Related Art
All patents, patent applications, patent publications, scientific articles, and the like, which will hereinafter be cited or identified in the present application, will hereby be incorporated by reference in their entirety in order to describe more fully the state of the art to which the present invention pertains.
FIG. 7 is a circuit diagram illustrating a conventional active clamp DC-DC converter. The conventional active clamp DC-DC converter is configured to exhibit a partial current resonance and a voltage quasi resonance. A circuit configuration and operations of this conventional active clamp DC-DC converter have been known.
Japanese Unexamined Patent Application, First Publication, No. 2001-224170 discloses an example of the conventional active clamp DC-DC converter. Japanese Unexamined Patent Application, First Publication, No. 2003-9528 discloses another example of the conventional active clamp DC-DC converter.
As shown in FIG. 7, the conventional active clamp DC-DC converter has the following circuit configuration. A PWM signal generating circuit (PWM) 41 is configured to generate a PWM (Pulse Width Modulation) signal. A first dead-time adding circuit (DT1) 51 is configured to receive the PWM signal from the PWM signal generating circuit (PWM) 41. The first dead-time adding circuit (DT1) 51 is configured to add a dead time to the PWM signal to generate a first deal-time added PWM signal. The dead time is a period of time during which both first and second switching devices Q1 and Q2 remain OFF or are prevented from turning ON. The first deal-time added PWM signal is transmitted from the first dead-time adding circuit (DT1) 51 through a first buffer circuit 61 to the first switching device Q1 as a first driving signal. The first switching device Q1 includes a power MOSFET. The power MOSFET further includes a MOSFET and a parasitic diode.
An inverter circuit 42 is configured to receive the PWM signal from the PWM signal generating circuit (PWM) 41. The inverter circuit 42 is configured to invert the PWM signal to generate an inverted PWM. A second dead-time adding circuit (DT2) 52 is configured to receive the inverted PWM signal from the inverter circuit 42. The second dead-time adding circuit (DT2) 52 is configured to add a dead time to the inverted PWM signal to generate a second deal-time added PWM signal. A level shifter 53 is configured to receive the second deal-time added PWM signal from the second dead-time adding circuit (DT2) 52. The level shifter 53 is configured to shift a voltage level of the second deal-time added PWM signal to generate a second level-shifted deal-time added PWM signal. The second level-shifted deal-time added PWM signal is transmitted through a second buffer circuit 61 to the second switching device Q2 as a second driving signal. The second switching device Q2 includes a power MOSFET. The power MOSFET further includes a MOSFET and a parasitic diode. The first and second switching devices Q1 and Q2 turn OFF alternately with the dead time.
The first switching device Q1 turns ON while the second switching element Q2 remaining OFF thereby causing a current flow from a DC power supply 10 through a primary coil P of a transformer T1 to the DC power supply 10. Namely, a DC voltage E generated by the DC power supply 10 is applied to the primary coil P of the transformer T1, so that an excitation current with a triangle waveform flows through the primary coil P of the transformer T1, whereby an electromagnetic energy is accumulated in the transformer T1. An ON-time of the first switching device Q1 is decided by a feedback signal of a photo coupler PC1. The feedback signal is an error signal that is defined between a detected signal and a reference voltage. The reference voltage has previously been given. The detected signal is an output voltage Vo that appears on a secondary side S of the transformer T1. The detected signal is detected by an output voltage detecting circuit 31. The error signal is transmitted from the secondary side S of the transformer T1 to the primary side P thereof through the photo coupler PC1. The output voltage Vo on the secondary side S of the transformer T1 is kept constant. The photo coupler PC1 includes a light emitting diode (PC-D), and a light receiving transistor (PC-TR).
The first switching device Q1 turns OFF while the second switching device remaining OFF, thereby causing a current flow into a first capacitor C1 while no current flowing through the primary side P of the transformer T1.
A voltage across the first switching device Q1 has a quasi resonant waveform between the first capacitor C1 and a first inductance Lp of the primary side P of the transformer T1. When a voltage across the first capacitor C1 reaches the sum of the DC power voltage E and a voltage VC2 across a second capacitor C2, a part of the current that have flown into the capacitor C1 is caused to flow into a parasitic diode DD2 of the second switching device Q2, whereby both the first and second capacitors C1 and C2 are charged. The electromagnetic energy that has been accumulated in the transformer T1 is discharged from the secondary side S of the transformer TI through an output rectifier diode D1 and a smoothing capacitor C3 to an output side.
During which the current flows through the parasitic diode DD2 of the second switching device Q2, the dead time has ended and the second switching device Q2 turns ON, thereby allowing the second switching device Q2 to perform as a zero volt switch. The current flowing through the parasitic diode DD2 of the second switching device Q2 is reduced and the polarity thereof is inverted, whereby a current is caused to flow through the MOSFET of the second switching device Q2. This current that flows through the MOSFET of the second switching device Q2 is a resonant current between the inductance Lp of the primary side P of the transformer T1 and a sum of the first and second capacitors C1+C2, whereby a part of a sine waveform can be observed.
The second switching device Q2 turns OFF while the first switching device Q1 remaining OFF, whereby a voltage appears across the first switching device Q1, wherein the voltage has a quasi resonant waveform of the inductance Lp and the first capacitor C1. The capacitance of the circuit configuration is reduced from the sum of the first and second capacitors C1 and C2 into the capacitor C1, thereby rising a resonant frequency.
The voltage across the first capacitor C1 reaches the zero volt, thereby causing a current flow through a parasitic diode DD1 of the first switch Q1 while no current flowing into the first capacitor C1. The dead time ends during which the current flows through the parasitic diode DD1 thereby causing the first switching device Q1 to turn ON so as to allow the first switching device Q1 to perform as the zero volt switch.
The above operations of the circuit will be repeated.
The circuit configuration of the conventional DC-DC converter needs the voltage isolator or the level shifter that is configured to control both the first and second switching devices Q1 and Q2 synchronously with each other, provided that the first and second switching devices Q1 and Q2 are largely different in those driving voltage. Namely, as shown in FIG. 7, the level shifter 53 is provided to control both the first and second switching devices Q1 and Q2. In consideration of a commercial power of 200V, a 600V or higher voltage level shifter is needed. In another case, a pulse transformer can be used as the voltage isolator. The voltage isolator such as the pulse transformer is generally expensive, whereby the DC-DC converter is also expensive.
As described above, the conventional active clamp DC-DC converter shown in FIG. 7 is configured to exhibit the partial current resonance and the voltage quasi resonance. The conventional active clamp DC-DC converter needs the 600V or higher voltage level shifter to control or drive the first and second switching devices Q1 and Q2 that are different in driving voltage by 600V or higher provided that a 200V commercial power system is used. The pulse transformer can also be used as the voltage isolator. The voltage isolator such as the pulse transformer is generally expensive, whereby the DC-DC converter is also expensive.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved active clamp DC-DC converter. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.